1 Scope
2 References
3 Definitions
4 Abbreviations
5 Source terminal packet parameters
5.1 Analogue/digital conversion clock
accuracy (free-running)
5.2 Packet information field size
5.3 Packet overhead
5.4 Source terminal delay
5.5 Source terminal delay variation
6 Packet network performance
parameters
6.1 Summary of network performance
parameters
6.2 Additional network parameters recommended
7 Destination terminal and overall
packet parameters
7.1 Discussion of destination packet
processing
7.2 Taxonomy of de-jitter
buffer types/parameters and models
7.3 System frequency offset, using
destination clock as reference
7.4 Packet loss concealment (type,
delay)
7.5 Overall delay (including source,
network and destination)
7.6 Time-scale discontinuities in
post-de-jitter and PLC stream
7.7 Overall (frame/packet) loss
(including network and destination)
Appendix I – Packet loss
distributions and packet loss models
I.1 Introduction
I.2 Common packet loss models
I.3 Example packet trace
I.4 Bibliography to Appendix I
Appendix II – Example adaptive
de-jitter buffer emulator
Appendix III – BIBLIOGRAPHY