Recommendation ITU-T G.709.3 (03/2024) Flexible OTN B100G long-reach interfaces
Summary
History
FOREWORD
Table of Contents
1 Scope
2 References
3 Definitions
     3.1 Terms defined elsewhere
          3.1.1 Terms defined in [ITU-T G.709]
          3.1.2 Terms defined in [ITU-T G.709.1]
          3.1.3 Terms defined in [ITU-T G.709.2]
          3.1.4 Terms defined in [ITU-T G.959.1]
          3.1.5 Terms defined in [ITU-T G.975.1]
     3.2 Terms defined in this Recommendation
4 Abbreviations and acronyms
5 Conventions
6 Introduction and applications
7 Structure and processes
     7.1 FlexO-x-DSH-m signal structure
     7.2 FlexO-x-DO-m signal structure
     7.3 Processing and information flow
8 FlexO frame
9 Overhead
10 FlexO mapping procedures
11 100G FlexO with staircase FEC frame structure
     11.1 FlexO-1-SC frame structure
     11.2 FlexO-1-SC bit rate and frame periods
     11.3 FlexO-1-SC overhead
          11.3.1 FlexO-1-SC FEC block alignment (FBA)
          11.3.2 Multi block alignment signal (MBAS)
     11.4 Staircase forward error correction (SC FEC)
12 200G FlexO with staircase FEC frame structure
     12.1 FlexO-2-SC frame structure
     12.2 FlexO-2-SC bit rate and frame periods
     12.3 FlexO-2-SC overhead
          12.3.1 FlexO-2-SC FEC block alignment (FBA)
          12.3.2 Multi block alignment signal (MBAS)
     12.4 Staircase forward error correction (SC FEC)
13 400G FlexO with staircase FEC frame structure
     13.1 FlexO-4-SC frame structure
     13.2 FlexO-4-SC bit rate and frame periods
     13.3 FlexO-4-SC overhead
          13.3.1 FlexO-4-SC FEC block alignment (FBA)
          13.3.2 Multi block alignment signal (MBAS)
     13.4 Staircase forward error correction (SC FEC)
14 FlexO-x-D
     14.1 FlexO-x-D frame and multi-frame structures
     14.2 FlexO-x-D Overhead
          14.2.1 Training sequence (TS)
          14.2.2 Pilot sequence (PS)
               14.2.2.1 8-bit block (k=8)
               14.2.2.2 4-bit block (k=4)
15 FlexO-x-DSH
     15.1 FlexO-x-DSH multi-frame and super-frame structures
          15.1.1 Multi-frame structure
          15.1.2 Super-frame structure
          15.1.3 Payload and FEC parity area
     15.2 FlexO-x-DSH bit rates and frame periods
     15.3 Overhead
          15.3.1 Multi-frame alignment signal (MFAS)
          15.3.2 Super-frame alignment signal (SFAS)
          15.3.3 Fixed stuff (FS)
     15.4 Mapping of FlexO-x-SC client into FlexO-x-DSH payload
          15.4.1 Scrambling
          15.4.2 119-bit FlexO-x-SC and PAD block numbering
          15.4.3 Convolutional interleaving
          15.4.4 Hamming soft decision forward error correction (DSH FEC)
          15.4.5 Mapping
               15.4.5.1 Mapping into FlexO-x-DSH for k=8 (DP-16QAM symbols)
               15.4.5.2 Mapping into FlexO-x-DSH for k=4 (DP-QPSK symbols)
     15.5 FOICx.k-DSH
          15.5.1 FOIC2.4-DSH lanes
          15.5.2 FOIC2.8-DSH lanes
          15.5.3 FOIC4.8-DSH lanes
          15.5.4 FOIC1.4-DSH lanes
16 FlexO-x-DO
     16.1 FlexO-x-DO multi-frame and super-frame structures
          16.1.1 Multi-frame structure
          16.1.2 Payload and FEC parity area
     16.2 FlexO-x-DO bit rates and frame periods
     16.3 Overhead
          16.3.1 Multi-frame alignment signal (MFAS)
          16.3.2 Fixed stuff (FS)
     16.4 Mapping of FlexO-x client into FlexO-x-DO payload
          16.4.1 OFEC block group (OFBG)
          16.4.2 OFBGk scrambling
          16.4.3 OFBGk structure representations
          16.4.4 Forward error correction
          16.4.5 Interleaving
               16.4.5.1 Intra-block interleaving
               16.4.5.2 Inter-block interleaving
          16.4.6 Mapping of OFBGk with parity (OFBGPk) into FlexO-x-DO
               16.4.6.1 Mapping of OFBGP8 into FlexO-x-DO (k=8) (DP-16QAM symbols)
               16.4.6.2 Mapping of OFBGP4 into FlexO-x-DO (k=4 DP-QPSK symbols)
     16.5 FOICx.k-DO
          16.5.1 FOIC1.4-DO lanes
          16.5.2 FOIC2.4-DO lanes
          16.5.3 FOIC2.8-DO lanes
          16.5.4 FOIC4.8-DO lanes
Annex A  Forward error correction using 512 × 510 staircase codes
Annex B  Adaptation of 512 × 510 staircase codes to 100G FlexO-1-SC FEC
     B.1 100G FlexO-1-SC bit and SC FEC specific base blocks mapping relationship
     B.2 100G FlexO-1-SC transmitter and receiver SC FEC processing
Annex C  Adaptation of 512 × 510 staircase codes to 200G|400G FlexO-x-SC FEC
     C.1 200G|400G FlexO-x-SC bit and SC FEC specific base blocks mapping relationship
     C.2 200G|400G FlexO-x-SC transmitter and receiver SC FEC processing
Annex D  Forward error correction using 10976 × 128 Hamming soft decision codes
     D.1 Forward error correction code
Annex E  Forward error correction using extended BCH(256,239) soft decision code
     E.1 Forward error correction code
Annex F  FlexO-x-D TS, PS and MFAS overhead values
     F.1 FlexO-x-DSH and FlexO-x-DO TS, PS and MFAS overhead values
          F.1.1 Training sequence (TS)
          F.1.2 Pilot sequence (PS)
               F.1.2.1 8-bit block (k=8)
               F.1.2.2 4-bit block (k=4)
          F.1.3 Multi-frame alignment signal (MFAS)
Annex G  Test Vectors
Appendix I  Error correction capability of the (128,119) Hamming soft decision code combined with the 512 × 510 staircase code
Appendix II  Error correction capability of a soft decision decoder for OFEC
Appendix III  FlexO-x-DO related equation illustrations and implementation considerations
     III.1 Introduction
     III.2 Illustration of equation 16-1
     III.3 Illustration of equations 16-2 and 16-3
     III.4 Illustration of equation 16-4
     III.5 Illustration of bit ordering in eUi, Wi, Vi and Ii
Appendix IV  Generic principles of forward error correction using blockwise-recursively-encoded open FEC
     IV.1 Open FEC codes: Specifications and basic properties
     IV.2 Permutation function
     IV.3 Decoding an open forward error correction code
Bibliography