1 Scope
2
References
3
Definitions and abbreviations
3.1 Definitions
3.2 Abbreviations
4
Reference models
4.1 STU‑x functional model
4.2 User plane protocol reference model
4.3 Application
models
5
Transport capacity
6
PMD layer functional characteristics
6.1 Data mode operation
6.1.1 STU data mode PMD reference model
6.1.2 TCM encoder
6.1.3 Channel precoder
6.1.4 Spectral shaper
6.1.5 Power backoff
6.2 PMD activation sequence
6.2.1 PMD activation reference model
6.2.2 PMD activation sequence description
6.2.3 Framer and scrambler
6.2.4 Mapper
6.2.5 Spectral shaper
6.2.6 Timeouts
6.3 PMD pre-activation sequence
6.3.1 PMD pre-activation reference model
6.3.2 PMD pre-activation sequence description
6.3.3 Scrambler
6.3.4 Mapper
6.3.5 Spectral shaper
6.3.6 PMMS target margin
6.4 G.994.1 pre-activation sequence
6.4.1 G.994.1 code point definitions
6.4.2 G.994.1 tone support
6.4.3 G.994.1 transactions
6.4.4 Operation with signal regenerators
7
PMS-TC layer functional characteristics
7.1 Data mode operation
7.1.1 Frame structure
7.1.2 Frame bit definitions
7.1.3 CRC generation (crc1 … crc6)
7.1.4 Frame synchronization
7.1.5 Scrambler
7.1.6 Differential delay buffer
7.2 PMS-TC activation
7.2.1 Activation frame
7.2.2 Activation scrambler
8
TPS-TC layer functional characteristics
8.1 Payload block data structure
8.2 Data interleaving in four-wire mode
9
Management
9.1 Management reference model
9.2 SHDSL performance primitives
9.2.1 Cyclical redundancy check anomaly (CRC
anomaly)
9.2.2 Segment anomaly (SEGA)
9.2.3 Loss of sync defect (LOSW defect)
9.2.4 Segment defect (SEGD)
9.2.5 Loop
attenuation defect
9.2.6 SNR margin defect
9.2.7 Loss of sync word failure (LOSW failure)
9.3 SHDSL line related performance parameters
9.3.1 Code violation (CV)
9.3.2 Errored second (ES)
9.3.3 Severely errored second (SES)
9.3.4 LOSW second (LOSWS)
9.3.5 Unavailable second (UAS)
9.3.6 Inhibiting rules
9.4 Performance data storage
9.5 Embedded operations channel
9.5.1 Management reference model
9.5.2 EOC overview and reference model
9.5.3 EOC startup
9.5.4 Remote
management access
9.5.5 EOC transport
9.5.6 Examples of virtual terminal control
functions
10 Clock architecture
10.1 Reference clock architecture
10.2 Clock accuracy
10.3 Definitions of clock sources
10.4 Synchronization to clock sources
11 Electrical characteristics
11.1 Longitudinal balance
11.2 Longitudinal output voltage
11.3 Return loss
11.4 Transmit power testing
11.4.1 Test circuit
11.4.2 Test circuit calibration
11.4.3 Total transmit power requirement
11.5 Signal transfer delay
12 Conformance testing
12.1 Micro‑interruptions
Annex A – Regional
requirements – Region 1
A.1 Scope
A.2 Test loops
A.3 Performance tests
A.3.1 Crosstalk margin tests
A.3.2 Impulse noise tests
A.3.3
Power spectral density of crosstalk disturbers
A.4 PSD masks
A.4.1 Symmetric PSD masks
A.4.2 Asymmetric 1.536 or 1.544 PSD mask
A.4.3 Asymmetric PSD masks for 768 or
776 kbit/s data rates
A.5 Region-specific functional characteristics
A.5.1 Data rate
A.5.2 Return loss
A.5.3 Span powering
A.5.4 Longitudinal balance
A.5.5 Longitudinal output voltage
A.5.6 PMMS target margin
Annex B – Regional requirements – Region 2
B.1 Scope
B.2 Test loops
B.2.1 Functional description
B.2.2 Test
loop topology
B.2.3 Test loop length
B.3 Performance testing
B.3.1 Test procedure
B.3.2 Test set-up definition
B.3.3 Signal and noise level definitions
B.3.4 Performance test procedure
B.3.5 Impairment generator
B.4 PSD masks
B.4.1 Symmetric PSD masks
B.4.2 Asymmetric 2.048 Mbit/s and
2.304 Mbit/s PSD masks
B.5 Region-specific functional characteristics
B.5.1 Data rate
B.5.2 Return loss
B.5.3 Span powering
B.5.4 Longitudinal balance
B.5.5
Longitudinal output voltage
B.5.6 PMMS target margin
Annex C – Regional requirements – Region 3
Annex D – Signal regenerator operation
D.1 Reference diagram
D.2 Start-up procedures
D.2.1 SRU‑C
D.2.2 SRU‑R
D.2.3 STU‑C
D.2.4 STU‑R
D.2.5 Segment failures and retrains
D.3 Symbol rates
D.4 PSD masks
Annex E – Application-specific TPS-TC framing
E.1 TPS-TC for clear channel data
E.2 TPS-TC for clear channel byte-oriented data
E.3 TPS-TC for unaligned DS1 transport
E.4 TPS-TC for aligned DS1/fractional DS1 transport
E.5 TPS-TC for European 2048 kbit/s digital unstructured
leased line (D2048U)
E.6 TPS-TC for unaligned European 2048 kbit/s digital
structured leased line (D2048S)
E.7 TPS-TC for aligned European 2048 kbit/s digital structured
leased line (D2048S) and fractional
E.8 TPS-TC for synchronous ISDN BRA
E.8.1 ISDN BRA over SHDSL frames
E.8.2 Mapping of ISDN B- and D-channels on
SHDSL payload channels
E.8.3 Multi-ISDN BRAs
E.8.4 ISDN BRA for lifeline service
E.8.5 Time slot positions of ISDN B- and D16-channels (EOC signalling)
E.8.6 Time slot positions of ISDN B- and D16-channels and the optional fast signalling channel
E.8.7 Signalling over the SHDSL EOC or the fast
signalling channel
E.8.8 S-Bus control
E.8.9 BRA termination reset
E.8.10 Transport of ISDN EOC messages over SHDSL
EOC
E.9 TPS-TC for ATM transport
E.9.1 Abbreviations
E.9.2 Reference model for ATM transport
E.9.3 Transport capacity and flow control
E.9.4 Operations
and maintenance
E.10 Dual bearer TPS-TC mode
E.10.1 Dual bearer clock synchronization
E.10.2 Dual bearer mode types
Appendix I – Test
circuit examples
I.1 Example crosstalk injection test circuit
I.2 Example coupling circuits for longitudinal balance and
longitudinal output voltage
I.3 Return loss test circuit
I.4 Transmit PSD/total power measurement test circuit
Appendix II – Typical characteristics of cables
II.1 Typical characteristics of cables for Annex B
Appendix III – Signal regenerator start-up description
III.1 STU‑R initiated start-up
III.2 STU‑C initiated start-up
III.3 SRU initiated start-up
III.4 Collisions and retrains
III.5 Diagnostic mode activation
Appendix IV – Bibliography